Analog-to-digital converters (ADCs) are used to convert an analog signal to a digitally coded signal. ADCs span a spectrum of designs that range from parallel flash-type converters employing multiple comparators that generally require a single clock cycle to determine all bits of resolution at one end of the spectrum, to a successive approximation-type converter that generally requires one clock cycle per bit of resolution at the other end of the spectrum. In order to achieve a high-speed conversion with little latency, a large number of comparators are employed in a flash converter. While flash converters achieve a fast conversion, they consume relatively large amounts of power. Successive approximation converters consume relatively less power than flash converters but introduce latency in converting an analog signal to a digitally coded signal. Successive approximation ADCs have been designed to operate on a fixed frequency clock, with the bit determination requiring the longest time being less than or equal to a clock cycle in duration. However, some time is wasted in a multibit successive approximation conversion since not all bit determinations require the same amount of time. With the successive approximation ADCs designed based on the worst-case bit determination time, all bit determinations other than the worst-case bit determination waste a portion of a clock cycle by completing the conversion of that bit in less time than the clock cycle duration.
What is needed is a technique to improve the speed of conversion of a successive approximation ADC such as by choosing the duration of a clock signal driving the successive approximation ADC based on the duration of time required for each bit determination.